This invention relates to a method for performing efficient and thorough memory testing on large arrays of computer system Random Access Memory (RAM) in single, contiguous blocks. The invention advantageously permits memory tests to be executed from high-speed cache memory existing on-board the central processing unit (CPU) of the computer system. Execution of the memory tests from the CPU cache permits effective testing of all of system RAM in one contiguous block while advantageously providing reasonable execution response time and performance.
For a system RAM memory test to be fully effective, the test must be capable of detecting functional memory faults of all varieties. Functional memory faults in computer system RAM come in several varieties. Typical types of faults include: "stuck-at" faults, where a memory cell is stuck at either a 1 or 0; "transition" faults, where one or more memory cells fail to undergo a 0 to 1, or 1 to 0 transition; "multiple access" faults, where more than one memory cell is accessed during a single read or write operation; and "coupling" faults, where a 0 to 1, or 1 to 0 transition in one memory cell causes a change in the contents of another memory cell.
In order to detect all of the possible types of memory faults, an effective memory test will test system RAM in a single, contiguous block. Without testing in single, contiguous blocks, certain types of faults (e.g., coupling faults) may go undetected. For example, if a memory cell at address 10000h is coupled to a memory cell at address 80000h, then a memory test that does not test the cell at address 10000h in the same contiguous block as the cell at 80000h will not detect the coupling fault.
Current operating system-based memory tests, such as those in off-the-shelf diagnostics software packages, have not been capable of detecting all types of memory, faults because they typically test system RAM in small blocks (e.g., 64 Kilobytes) or, alternatively, in two blocks. To date, single-block, contiguous memory testing has been accomplished via a personal computer system's Power On Self Test (POST) memory tests or via diagnostic memory tests residing in Read Only Memory (ROM) or flash memory, both of which suffer from slow access times. In order to achieve even marginally acceptable performance under this approach, many POST memory tests have been modified to run from system memory, rather than from much slower ROM or flash memory. While clearly boosting performance, this approach prevents a fully effective memory test on all of system RAM because the memory test code resides in system RAM, thereby preventing a complete test of the entire system RAM in one contiguous block.
Methods of memory testing used thus far have either failed to test adequately for all types of memory faults or performed too slowly due to execution of memory test code residing in slow access speed ROM or flash memory. Memory test code residing in the same system RAM address range as that being tested inhibits testing the entire range of system RAM in one contiguous block. On the other hand, performance is less than satisfactory when the memory test code is executed from slow access ROM or flash memory. As computer systems are equipped with more and more contiguous memory, the amount of time required to test large contiguous blocks of system memory is becoming an even more critical issue. Because of the slower access times of ROM or flash memory, memory test code executes so slowly that it is often impractical or undesirable to test large contiguous blocks of system memory.
Therefore, what is needed is a method for testing all of system RAM in one contiguous block, while, at the same time, providing reasonable performance.